ELA is an exciting, fast-paced company that is focused on a high-growth segment of the electronic chip design market. We are an extremely motivated and talented team of professionals that work directly with our customers to ensure they can successfully build their next SoC design.

We are looking for RTL to GDSII engineers with strong communication skills, have a self starting attitude, play well in a team environment, and have multiple ASIC/COT project completion experiences under their belt.

ELA has three design centers (Santa Clara, Ottawa and Boston) and are looking to fulfill any of these positions in these areas. All these positions are senior positions and require at least 8 years of experience and with appropriate degrees.

You will be able to generate functional specifications and interpret design and standards documents. This will include coding of various functionalities and taking these designs through synthesis using various methods and tools. Using STA you will be able to identify critical paths or regions and be able to use Formal verification to confirm your design. You should be able to work independently.

By either using top down or hierarchical approaches, you will be capable of the complete flow. This will involve synthesis of the logic, floorplanning, I/O placement and cell/macro placement. You will specify and implement the clock tree synthesis as well as the power distribution scheme for all the different areas – core, I/O and special macros. Global and detailed route will also be undertaken. STA and Formal verification will be used to ensure design verification as well as the LVS/DRC verification.

We are looking for experienced candidates who have detailed knowledge in signal integrity, noise analysis and power analysis. This will tie in with your experience in STA and violation closure fixes as well as being able to perform LVS/DRC analysis and fixes. Knowledge of formal verification would also be a benefit.

You will develop test specifications and implementation strategies and then be responsible for the test logic insertion including JTAG, boundary scan, memory BIST, scan and logic BIST. You will use STA to identify critical test paths and logic areas. After running vector generation, simulation and qualification you will help bring up the test program on the ATE. Yield data analysis will also play a large part in this job to improve our customer’s bottom line.