EL & Associates, Inc. specializes in integrated solutions for design (RTL to GDSII), Design-For-Test (DFT) and Design-For-Manufacturing (DFM) services for ASIC, ASSP, COT, and FPGA. We engage with customers from RTL phase to silicon prototype. The ELA methodology is optimized to manage risk in design, manufacture and product deployment. ELA has successfully completed over 750 designs to date.

Headquartered in Pleasanton, California since 1989, the company has design centers in Santa Clara, California and Ottawa, Canada. The Boston area design center will be open in early 2006.

• chip implementation project management, setting up and executing overall methodology;
• chip design from RTLs to gates, verification of functionality, static timing analysis, formal verification of equivalences;
• chip test structure design and insertion. JTAG boundary scan, full/partial SCAN, memory BIST, logic BIST, PLL, DLL, SERDES, specialized I/O, microprocessor, other IP;
• chip prototyping/manufacturing test vector creation and validation;
• chip qualification/testing support and yield enhancement;

• SERDES,
• high-speed I/O interfaces
• microprocessor cores
• PLLs
• RAMs (tested using BIST, scan, and functional patterns)
• various I/O cells (standard CMOS, NTL, GTL, LVDS, PECL, etc)

We reduce productization risks and schedules for the chip signoff flow by providing a turnkey solution. Schedule reductions on the order of months have been achieved previously. ELA will help you to bridge the gap between design and manufacturing organizations. We can also help you to manage and improve the all important chip supply chain.

Our customers include both small startup companies and well-established technology leaders in a variety of industry segments.